Cadence 南京招模拟芯片设计经理和工程师

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1.　　Position: Design Manager, Serdes R&D　
Location: Nanjing
Job description
Responsible for design, layout, verification, and characterization of high-
speed transceiver elements, TIAs, limiting amplifiers, I/Os, equalizers,　
high-speed CML, and other SerDes/CDR/PLL building blocks at data rates of　
25Gb/s and higher.　
You will work as a part of a Serdes team in a dynamic startup environment,　
taking an active role in design implementation, design reviews, contributing　
to product definition, proposing and evaluating technical solutions, writing　
design specifications and test requirement documents, etc.　
The ideal candidate is a hands-on self-starter who is able to develop design　
based on input from colleagues, customers, and industry and who can　
effectively manage his or her own time to take projects to completion with　
limited supervision and guidance.
DESIRED QUALIFICATIONS
•　　10+ years’ experience for Bachelor in Electrical Engineering or 7+　
years’ experience for M.S in Electrical Engineering.
•　　5+ years of working/research experience in high-speed CMOS SerDes design (
CTLEs, TIAs, PLLs, DFEs, etc.), M.S in Electrical Engineering and Ph.D.　
preferred
•　　Have experience designing in advanced CMOS (65nm or below) at data rates　
of at least 10Gb/s and/or RF circuits operating at 5GHz or above
•　　Proficient with Cadence design environment and mixed-signal simulation (
ADE, Layout, AMS), mixed-signal simulation (AMS), EM simulation (such as EMX)
•　　Good understanding of high-speed layout considerations, such as　
parasitics, crosstalk isolation, supply and bias distribution, etc.
•　　Working knowledge of theoretical and practical aspects of electro-
magnetic structures including transmission lines, spiral inductors, resonant　
circuits, etc. (HFSS experience is a plus)
•　　Experience with precision analog and mixed-signal circuits is a plus
•　　Able to assume responsibility for a variety of technical tasks and to　
work independently
•　　Able to be hands-on at all levels of design, with the ability to verify,　
test, and characterize own designs
•　　Good communication and presentation skills
•　　Familiar with USB,MIPI, HDMI, DP, PCIe, 10GKR, CCIX and other standard.

2.　　Position: Principal Design Engineer, Serdes R&D　
Location: Nanjing
Job description
Responsible for design, layout, verification, and characterization of high-
speed transceiver elements, TIAs, limiting amplifiers, I/Os, equalizers,　
high-speed CML, and other SerDes/CDR/PLL building blocks at data rates of　
25Gb/s and higher.　
You will work as a part of a Serdes team in a dynamic startup environment,　
taking an active role in design implementation, design reviews, contributing　
to product definition, proposing and evaluating technical solutions, writing　
design specifications and test requirement documents, etc. The ideal　
candidate is a hands-on self-starter who is able to develop design based on　
design specification and schedule.
DESIRED QUALIFICATIONS
•　　10+ years’ experience for Bachelor in Electrical Engineering or 7+　
years’ experience for M.S in Electrical Engineering.
•　　5+ years of working/research experience in high-speed CMOS SerDes design (
CTLEs, TIAs, PLLs, DFEs, etc.), M.S in Electrical Engineering and Ph.D.　
preferred
•　　Have experience designing in advanced CMOS (65nm or below) at data rates　
of at least 10Gb/s and/or RF circuits operating at 5GHz or above
•　　Proficient with Cadence design environment and mixed-signal simulation (
ADE, Layout, AMS), mixed-signal simulation (AMS), EM simulation (such as EMX)
•　　Good understanding of high-speed layout considerations, such as　
parasitics, crosstalk isolation, supply and bias distribution, etc.
•　　Working knowledge of theoretical and practical aspects of electro-
magnetic structures including transmission lines, spiral inductors, resonant　
circuits, etc. (HFSS experience is a plus)
•　　Experience with precision analog and mixed-signal circuits is a plus
•　　Able to assume responsibility for a variety of technical tasks and to　
work independently
•　　Able to be hands-on at all levels of design, with the ability to verify,　
test, and characterize own designs
•　　Good communication
•　　Familiar with USB, MIPI, HDMI, DP, PCIe, 10GKR, CCIX and other standard.

3.　　Position: Lead Design Engineer, Serdes R&D
Location: Nanjing
Job description
Responsible for design, layout, verification, and characterization of high-
speed transceiver elements, TIAs, limiting amplifiers, I/Os, equalizers,　
high-speed CML, and other SerDes/CDR/PLL building blocks at data rates of　
25Gb/s and higher.　
You will work as a part of a Serdes team in a dynamic startup environment,　
taking an active role in design implementation, design reviews, contributing　
to product definition, proposing and evaluating technical solutions, writing　
design specificaons and test requirement documents, etc.　
You are expected to develop the design according to the design specification,
provide your input and feedback to the design specification according to　
your own experience and work with other team member together to achieve the　
performance and schedule requirement of the product.
DESIRED QUALIFICATIONS
•　　6+ years’ experience for Bachelor in Electrical Engineering or 3+ years’
experience for M.S in Electrical Engineering.
•　　Working/research experience in high-speed CMOS SerDes design (CTLEs, TIAs,
PLLs, DFEs, etc.),　
•　　Nice to have experience designing in advanced CMOS (65nm or below) at　
data rates of at least 10Gb/s and/or RF circuits operating at 5GHz or above
•　　Proficient with Cadence design environment and mixed-signal simulation (
ADE, Layout, AMS), mixed-signal simulation (AMS), EM simulation (such as EMX)
•　　Good understanding of high-speed layout considerations, such as　
parasitics, crosstalk isolation, supply and bias distribution, etc.
•　　Working knowledge of theoretical and practical aspects of electro-
magnetic structures including transmission lines, spiral inductors, resonant　
circuits, etc.　
•　　Experience with precision analog and mixed-signal circuits is a plus
•　　Able to assume responsibility for a variety of technical tasks and to　
work independently
•　　Able to be hands-on at all levels of design, with the ability to verify,　
test, and characterize own designs. Good communication
•　　Familiar with USB,MIPI, HDMI, DP, PCIe, 10GKR, CCIX and other standard.

4.　　Position: Design　and Layout Engineer, Serdes R&D　
Location: Nanjing
Job description
Responsible for design, layout, verification, and characterization of high-
speed transceiver elements, TIAs, limiting amplifiers, I/Os, equalizers,　
high-speed CML, and other SERDES/CDR/PLL building blocks at data rates of　
25Gb/s and higher.　
You will work as a part of a SERDES team in a dynamic startup environment,　
taking an active role in design implementation, design reviews, contributing　
to product definition, proposing and evaluating technical solutions, writing　
design specifications and test requirement documents, etc.
You are expected to develop the design according to the design　
specification, provide your input and feedback to the design specification　
according to your own experience and work with other team member together to　
achieve the performance and schedule requirement of the product. You are　
expected to learn the new technology proactively and grow with the team to　
be the world leading engineer in SERDES design.
DESIRED QUALIFICATIONS
•　　3+ years’ experience for Bachelor in Electrical Engineering or M.S in　
Electrical Engineering.　
•　　Candidate should have working knowledge of a set of common SerDes　
standards and their electrical requirements, and a thorough understanding of　
jitter.　
•　　Nice to have experience designing in advanced CMOS at data rates of at　
least 10Gb/s and/or RF circuits operating at 5GHz or above
•　　Proficient with Cadence EDA tool set　
•　　Good understanding of high-speed layout considerations　
•　　Experience with precision analog and mixed-signal circuits is a plus
•　　Proactive quick learner and good communication skill
•　　Able to be hands-on at all levels of design, with the ability to verify,　
test, and characterize own designs