Cadence 南京招聘数字后端设计工程师

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Title: Senior Design Engineer - Backend

Position Description:　　　
　　Focus on high speed digital DDR, HBM and other memory related IP physical　
implementation.　

Position Requirement:　　　
　　Have good physical design experiences in the digital implementation　
domain including Floorplan, P&R, Physical verification, DFM.　
　　Have a solid background in circuits, electronics & physics & should be　
very willing to learn new technology for advance node and design methodology.
　　Skilled in scripting language, such as Perl, C shell, Makefile.
　　Feeling responsible for technical delivery, good team played, design　
quality/schedule focus.
　　Master degree with related physical design experience.
　　Self-motivated, able to work as a team player, excellent verbal and　
written communication skills in English.

Title: Lead Design Engineer - Backend

Position Description:　
　　Perform physical design implementation, including floor planning, power　
grid design, place and route, clock tree synthesis, timing closure, power/
signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR　
signoff, DFM Closure.
　　The candidate will have the opportunity to work on many varieties of　
challenging designs, i.e. low power and high speed design. The responsibility
includes participating in or leading next generation PHY IP physical design,
methodology and flow development.　
　
Position Requirements:　　　　
　　Bachelor degree with 5+ years of applicable experience, Master degree　
with 3+ years of applicable experience in electrical engineering,　
microelectronics.　
　　Experienced with ASIC design flow, hierarchical physical design　
strategies, and methodologies and understand deep sub-micron technology　
issues.　
　　Solid knowledge on Low Power Design, static timing analysis, EM/IR-Drop/
crosstalk analysis, physical verification, DFM.　
　　Successful track records of taping out complex chips at various　
technology nodes. Experience with advanced nodes at 16nm and below is　
preferred.
　　Automation and programming-minded, solid coding experience in Makefile/
Tcl/Tk/Perl.　
　　Self-motivated, able to work as a team player, excellent verbal and　
written communication skills in English.



Title: Principal Physical Design Engineer - Backend　

Position Description:
　　Perform physical design implementation, including synthesis, floor　
planning, power grid.
　　design, place and route, clock tree synthesis, timing closure, power/
signal integrity signoff.
　　Physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and　
physical design.
　　Project management experience.
　　The candidate will have the opportunity to work on many varieties of　
challenging designs.
　　Low power and high speed design. The responsibility includes　
participating in or leading.
　　Next generation physical design, methodology and flow development.

　　 Position Requirements:
　　Bachelor degree with 8+ years of applicable experience, Master degree　
with 6+ years of applicable experience in electrical engineering,　
microelectronics.　
　　Experienced with ASIC design flow, hierarchical physical design　
strategies, and methodologies and understand deep sub-micron technology　
issues. Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-
Drop/crosstalk analysis, formal verification, physical verification, DFM.　
　　Successful track records of taping out complex chips at various　
technology nodes. Experience with advanced nodes at 16nm and below is　
preferred.
　　Automation and programming-minded, solid coding experience in Makefile/
Tcl/Tk/Perl.　
　　Self-motivated, able to work as a team player, excellent verbal and　
written communication skills in English.