Cadence 南京招聘数字前端设计工程师

更多职位信息敬请关注Cadence公众微信平台：Cadence微招聘

If you have interest, PLS send your update CV to job_china@cadence.com

Title: Senior Design Engineer – Frontend
　
Position Description:　
Deliver/implement IP and SoC chip. The engineer should be able to act as a　
good team member and contributor
Specific duties include:
　　Proficiency in logic design, simulation, synthesis, STA and testing.
　　Proficiency in Verilog and its simulation environment.
　　Good knowledge of problem analysis/solving.

Position Requirements:　
　　Master degree with 0~2 years of applicable experience in electrical　
engineering, microelectronics, comparable engineering science or solid state　
physics.　
　　Essential that the individual demonstrates strong communication, verbal　
and written.　
　　Self-motivated, able to work as a team player, excellent verbal and　
written communication skills in English.

Title: Lead Design Engineer – Frontend

Position Description:　
　　Deliver/implement IP and SoC chip. The engineer should be able to act as　
a strong team member and contributor.　

Specific duties include:
　　Proficiency in logic design, simulation, synthesis, STA and testing
　　Proficiency in Verilog and its simulation environment
　　Good knowledge of IC design
　
Position Requirements:　
　　Essential Qualifications: Must have Bachelor degree with 6+ years of　
applicable experience, Master degree with 3+ years of applicable experience　
in electrical engineering, microelectronics, comparable engineering science　
or solid state physics.　
　　Essential that the individual demonstrates strong communication, verbal　
and written.
　　Requires good communication skills in English.
　　Will have demonstrated successful completion of 3+ design projects as an　
individual contributor
　　Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols and have DDR project　
design experience is a plus
　　Self-motivated, able to work as a team player, excellent verbal and　
written communication skills in English.

Title: Principal Front-end Design Engineer

Position Description:　
　　Deliver/implement IP and SoC chip. The engineer should be able to act as　
a strong team member and contributor.　

Specific duties include:
　　Be responsible for building and leading a high-performance IC design team,
owning the IC micro-architecture, package and test platform development,　
refining the EDA design flow
　　Proficiency in logic design, simulation, synthesis, STA and testing
　　Proficiency in Verilog and its simulation environment
　　Good knowledge of IC design
　　At least five years’ experience driving complex IC development projects,　
excellent communication skills and the uncanny ability to both lead and　
contribute in a cooperative team environment.　
　
Position Requirements:　
　　Essential Qualifications: Must have Bachelor degree with 8+ years of　
applicable experience, Master degree with 5+ years of applicable experience　
in electrical engineering, microelectronics, comparable engineering science　
or solid state physics.　
　　Essential that the individual demonstrates strong communication, verbal　
and written.
　　Requires good communication skills in English.
　　Technically manages projects with other Design Engineering team members　
and may
participate in cross functional projects
　　Continues to develop leadership and mentoring skills in anticipation of　
leading multiple
projects across teams
　　Self-motivated, able to work as a team player, excellent verbal and　
written communication skills in English.